In general, a semiconductor device includes a number of integrated electronic circuits, and a plurality of semiconductor devices may be fabricated on a single wafer. However, delay times of elements of the semiconductor device(s) may change over time due to variations of fabrication processes. In other words, delay times of semiconductor device elements may be longer and/or shorter than those intended by design.
Conventionally, a plurality of semiconductor devices (e.g., semiconductor memory devices) may be provided on a single wafer, and test circuits may be disposed in spaces between the semiconductor devices to measure delay times of various elements.
FIG. 1 shows construction of a test circuit of a conventional semiconductor device. Referring to FIG. 1, the test circuit includes a power supply voltage pad PA1, a ground voltage pad PA2, output pads PB1 to PBn, and first to n-th ring oscillators 10-1 to 10-n. The first to n-th ring oscillators 10-1 to 10-n include first to n-th delay circuits DL1 to DLn, respectively. In FIG. 1, each of the first to n-th delay circuits DL1 to DLn includes different elements.
A method for measuring delay times of the respective elements of the first to n-th delay circuits DL1 to DLn will now be described with reference to FIG. 1. When a power supply voltage and a ground voltage are applied from a test apparatus (not shown) to the power supply voltage pad PA1 and the ground voltage pad PA2, respectively, the first to n-th ring oscillators 10-1 to 10-n generate clock signals at the respective output pads PB1 to PBn. The test apparatus receives the clock signals from the output pads PB1 to PBn and measures cycles of the clock signals so that the test apparatus can calculate delay times of the respective elements of the first to n-th delay circuits DL1 to DLn.
A typical ring oscillator includes an odd number of inverters that are cascade-connected. For example, assuming that each of the first to n-th delay circuits DL1 to DLn includes 7 cascade-connected inverters and a designed delay time of each of the inverters is preset to 1 nsec, the total delay time of the 7 inverters should be 7 nsec and thus, the cycle of each of the clock signals should be 14 nsec. If each of the clock signals output through the output pads PB1 to PBn has a cycle of 15 nsec, it can be determined that each of the inverters has a cycle of 15/14 nsec that is greater than the designed delay time (i.e., 1 nsec).
Because the conventional test circuit is disposed in the space between the semiconductor devices on the wafer, however, the test circuit can be measured only in the wafer state and cannot be measured during or after a packaging process.